The clock signal generator using crystal oscillator is widely used in all kinds of digital electronic equipment, such as personal computer, network communications devices, computer peripherals and the consumer products, to generate clock signals. Clock signals generated by clock generator are used as reference of synchronization for the electronic equipment. However, the intensive operations of the digital circuitry used in the electronic equipment generate radiation that causes electromagnetic interference (EMI) emissions, too. According to the regulations of most countries, EMI generated by electronic equipment needs to be eliminated by using additional filter or shielding, before the electronic equipment may be put to the market. In these countries, EMI is regulated against the “peaking” of electromagnetic emissions, rather than their total energy. Among all kinds of EMI suppression technology, the spread spectrum clocking (SSC) technology is most popular. The SSC technology periodically modulates the frequency of the clock signals, such that the peak energy of clock signals is spread into wider and flatter peaking spectrum.
The phase-locked loop (PLL) is widely used as a standard built-in clock signal generator for modern electronic systems to provide frequency synthesis functions based upon precision clock sources such as the crystal oscillator. Embedding the spread spectrum clock generator in PLL is thus a desirable feature to save the implementation cost, in the modulation of EMI in order to comply with applicable EMI regulations.
Hardin et al. disclosed a spread spectrum clock generator and associated method in their U.S. Pat. No. 5,488,627. The invention of Hardin et al. provides the basic infrastructure of embedding a spread spectrum clock generator in the phase-locked loop. In their invention, the phase-locked loop modulates a voltage controlled oscillator (VCO), such that the output signals are compatible with the input of the phase detector. The spread spectrum clock generator frequency modulates the clock pulses with a periodic waveform having a predetermined period and a predetermined frequency deviation profile as a function of the predetermined period.
After the invention of Hardin et al., many phase-locked loops with spread spectrum clock generator were disclosed. Among them, Sha's U.S. Pat. No. 6,377,646 disclosed a spread spectrum at phase lock loop feedback path. According Sha's invention, outputs of the phase-locked loop are fed back via a feedback divider to a phase detector positioned at front end of the phase-locked loop, as input component of the phase detector. Outputs of the feedback divider are given to a spread spectrum clock generator. The spread spectrum clock generator comprises a counter, a 4 bit phase-locked spread spectrum clock generator, ROM and an adder. The output of the feedback divider provides a modulated waveform to the output of the VCO, such that the output of the VCO is spread within a predetermined bandwidth. As a result the peaking value of the clock signal is reduced. In this invention, the spread spectrum clock generator generates an adjustment factor to the feedback divider, so to determine the width and the waveform of the spread spectrum.
In the '646 patent, a programmable counter is used to give a value, taking the output of the feedback divider as basis. The output of the counter is used to select applicable codes from the ROM. The selected code is added with a base number and the result is supplied to the feedback divider to adjust a value in the feedback divider. The ROM codes are generated by a least-mean-squared (LMS) error method.
In Sha's invention, the spread spectrum clock generator comprises a counter, a ROM, a ROM decoder, an adder and a divider. The decoding involved complicated circuit or operations. The SSC generator of Sha's invention is expensive in cost and complicated in circuit or software design.
It is thus necessary to provide a low cost phase-locked loop having spread spectrum clock generator.
It is also necessary to provide a simplified phase-locked loop having spread spectrum clock generator.